5th International Workshop on Mixed Criticality Systems 

at the Real Time Systems Symposium
 (RTSS 2017)

Paris, France 
5th December 2017

Important dates:

Submission deadline: 1st Oct. 2017 (extended and firm) (23:59 GMT-12)
Notification of acceptance: 25th Oct. 2017
Final version due: 31st Oct. 2017
Workshop: 5th Dec. 2017
RTSS: 6th - 8th Dec. 2017

Program Chairs: 

  • Arvind Easwaran   
    Nanyang Technological University, Singapore
    Email: arvinde@ntu.edu.sg 
  • Kunal Agrawal   
    Washington University in St. Louis, St. Louis MO, USA
    Email: kunal@wustl.edu 

Steering Committee: 

Program Committee: 

  • Dirk Ziegenbein   
        Bosch Research, Germany 
  • Zhishan Guo   
        Missouri University of Science and Technology, USA 
  • Luca Santinelli   
        Onera, France 
  • Jing Li   
        New Jersey Institute of Technology, USA 
  • Leandro Soares Indrusiak   
        University of York, UK 
  • Geoffrey Nelissen   
        ISEP, Portugal 
  • Martina Maggio   
        Lund University, Sweden 
  • Jaewoo Lee   
        KAIST, Korea 
  • Xiaoting Li   
        ECE Paris, France 
  • Tam Chantem   
        Virginia Tech, USA 
  • Pontus Ekberg   
        Uppsala University, Sweden 

Previous WMC:


Workshop on Mixed Criticality Systems 2017



WMC publishes informal proceedings. The authors retain the copyright to their work and are free to submit extended versions to a conference or journal.

Workshop Proceedings: pdf


WMC’s goal is to promote sharing of new ideas, experiences and information about research and development of mixed criticality real-time systems.

The workshop aims to bring together researchers working in fields relating to real-time systems with a focus on the challenges brought about by the integration of mixed criticality applications onto singlecore, multicore and manycore architectures. These challenges are cross-cutting.

To advance rapidly, closer interaction is needed between the sub-communities involved in real-time scheduling, real-time operating systems / runtime environments, and timing analysis. The workshop aims to promote understanding of the fundamental problems that affect Mixed Criticality Systems (MCS) at all levels in the software/hardware stack and crucially the interfaces between them.

The workshop will promote lively interaction, cross fertilisation of ideas, synergies, and closer collaboration across the breadth of the real-time community, as well as attracting industrialists from the aerospace, automotive and other industries with a specific interest in MCS. Original unpublished papers on all aspects of mixed criticality real-time systems are welcome.

Themes include, but are not limited to:

  • Task and system models for MCS on singlecore, multicore, and manycore platforms.
  • Scheduling schemes and analyses for MCS, including the integration of appropriate models of overheads and delays.
  • Run-time environments and support for MCS, including data exchange and synchronisation across criticality levels, and issues relating to criticality mode.
  • Analysis of worst-case execution times (WCET) relating to MCS.
  • Mixed criticality communications mechanisms and analysis, including Network-on-Chip support.
  • Probabilistic analysis techniques for MCS.

The scope of the workshop is real-time, mixed criticality systems. Papers that do not relate to real-time behaviour (i.e. are solely about security or safety aspects of MCS) will be considered as out of scope.



Submissions must be in the same format as in the final proceedings   (6 pages maximum, 2 columns, 10 pt, US Letter) compliant with IEEE formatting guidelines. Papers exceeding the page limit will not be reviewed.

The material must be unpublished and not under submission elsewhere. By submitting a paper, the authors confirm that if the paper is accepted, at least one author will register for the WMC 2017 workshop by the special registration deadline set in the notification of acceptance, and present the paper at the workshop in person.

Papers must be submitted electronically in PDF format.